Altera Cyclone II ES2C5T144 FPGA Dev Board (HCDVBD0026)

Altera development boards and accessories
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Altera Cyclone II ES2C5T144 FPGA Dev Board (HCDVBD0026)

Post by admin » Fri Aug 12, 2016 9:14 am


This development board is a low cost way to get into the world of FPGAs and programmable logic. Based on a 144 pin Altera Cyclone II (EP2C5ST144C8N) device this board is a significant step up from our popular MAX II CPLD development board (HCDVBD0006). It features standard 0.1" pitch breakout headers for the devices 89 usable I/O cells, on-board 50MHz crystal oscillator which provides the FPGA's internal clock source, on-board 3.3V & 1.2V regulators with 2.1mm DC power socket, user LED's and both JTAG and ASP with EPCS device programming headers which are directly compatible with our Altera USB programmer (see item HCDVBD0007).


Board Features:

Breakout headers for all usable I/O
On-board 3.3V & 1.2V regulators.
Single 5V power source via 2.1mm DC socket
3x programmable user LEDS connected to pins 3, 7 & 9
Power LED
On-board 50MHz oscillator connected to pin 17
Reset button
JTAG interface
ASP serial programming interface with on board EPCS4 storage
Compatible with the Altera Quartus 2 and free web edition software

FPGA Features:

Number of Logic Elements: 4608 (16 LE's per block)
Number of 4K bit memory blocks: 26 (119,808 total bits)
Number of embeded multipliers: 13 (can be configured as 2 x 9 bit or 1 x 18 bit)
Number of PLL's: 2
Maxium usable IO: 89

Please note: Depending on your design, FPGAs can consume a large amount of power. If you have a complex design it may exceed the capabilities of the on-board regulators. In this case you should power the development board via the power header pins.

Recommended accessories:

Hobby Components Altera Blaster compatible CPLD/FPGA programmer: ... compatible

USB to 2.1mm power lead: ... -jack-plug


Software tools:

Altera Quartus II Web Edition (13.0) ... rm=windows

Altera Quartus Prime Lite Edition (15.1)

Verilog 'Blink' Example:

Code: Select all

module ledtest(sys_clk,led);

input sys_clk;
output [2:0] led;
reg	[25:0] count;
reg [2:0] led = 3'b101;

always @(posedge sys_clk)
		count <= count + 1;
		if(count == 26'b11_1111_1111_1111_1111_1111_1110)
			led <= ~led; 
			led <= led;




Each time i remove power my design is lost, how can I permanently program the FPGA?

The FPGA has no non-volatile storage capability. This is actually normal for these types of devices. However this development board does include an EPCS (EPCS04) IC. This is a custom device which is designed to store your design and then program the FPGA automatically as power is applied to the board. To program the EPCS device follow these steps:

1) Connect your programmer to the ASP header instead of the JTAG header. This will connect your programmer to the EPCS device instead of the FPGA

2) Open up the programmer window in Quartus (Tools->programmer) and in the window that opens up select 'Active Serial Programming' instead of JTAG for the programmer mode.

3) Next click the 'Add device button' and a new window will open. Under the Device name list check the 'EPS4' check box and then close the window by clicking the OK button.

4) In the main programmer window click the 'Change File' button and in the window that opens up navigate to your project area and select the file containing your design. Note that when programming the EPCS device you will need to select the file ending in .pof instead of the .sof file used for programming the FPGA.

5) In the main programmer window you can now check the program, verify, blank check, examine, or erase check boxes as required.

Disclaimer: Libraries, example code, and diagrams are provided as an additional free service by Hobby Components and are not sold as part of this product. We do no provide any guarantees or warranties as to their accuracy or fitness for purpose.

Descriptions and diagrams on this page are copyright Hobby Components Ltd and may not be reproduced without permission.
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Posts: 1
Joined: Mon Mar 27, 2023 1:29 pm

Re: Altera Cyclone II ES2C5T144 FPGA Dev Board (HCDVBD0026)

Post by iandiment » Mon Mar 27, 2023 1:49 pm

Hi, I'm trying to use the PLLs in this FPGA. I'm using megawizard plug-in manager to create the Verilog for this. I am starting with a test of PLL with external clock output option (tested both with board built in clock as input on pin 17 and with external input from pin 21), no other parts of any design loaded. However, when I loaded the design:

Using pin 31 for external output from c0. Using pin 3 to drive LED for lock indication. (LED out is pin high/locked).

1. I get lock but output waveform is massively distorted. it is at the right frequency.
2. This maybe related. Power consumption of board jumps from 40mA to 230mA and 1.2 Volt regulator (U4 on bottom) starts getting hot. 1.2V regulator feeds the analogue PLL power supplies input (per PLL data sheet and per schematic included here on this forum post).

I know that loading a design will increase current comsumption but these seems a lot for 1 PLL on it's own and with output like it is.

What am I doing wrong? Or is there a fault with this board. It's like something's shorted in the PLL and it's pulling too much current and it's distoring the output. (where peaks of wave form should be is flatned to a large dip).


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