Reply to topic  [ 1 post ] 
Altera Cyclone II ES2C5T144 FPGA Dev Board (HCDVBD0026) 
Author Message
Site Admin

Joined: Sun Aug 05, 2012 4:02 pm
Posts: 650
Post Altera Cyclone II ES2C5T144 FPGA Dev Board (HCDVBD0026)

This development board is a low cost way to get into the world of FPGAs and programmable logic. Based on a 144 pin Altera Cyclone II (EP2C5ST144C8N) device this board is a significant step up from our popular MAX II CPLD development board (HCDVBD0006). It features standard 0.1" pitch breakout headers for the devices 89 usable I/O cells, on-board 50MHz crystal oscillator which provides the FPGA's internal clock source, on-board 3.3V & 1.2V regulators with 2.1mm DC power socket, user LED's and both JTAG and ASP with EPCS device programming headers which are directly compatible with our Altera USB programmer (see item HCDVBD0007).


Board Features:

Breakout headers for all usable I/O
On-board 3.3V & 1.2V regulators.
Single 5V power source via 2.1mm DC socket
3x programmable user LEDS connected to pins 3, 7 & 9
Power LED
On-board 50MHz oscillator connected to pin 17
Reset button
JTAG interface
ASP serial programming interface with on board EPCS4 storage
Compatible with the Altera Quartus 2 and free web edition software

FPGA Features:

Number of Logic Elements: 4608 (16 LE's per block)
Number of 4K bit memory blocks: 26 (119,808 total bits)
Number of embeded multipliers: 13 (can be configured as 2 x 9 bit or 1 x 18 bit)
Number of PLL's: 2
Maxium usable IO: 89

Please note: Depending on your design, FPGAs can consume a large amount of power. If you have a complex design it may exceed the capabilities of the on-board regulators. In this case you should power the development board via the power header pins.

Recommended accessories:

Hobby Components Altera Blaster compatible CPLD/FPGA programmer:

USB to 2.1mm power lead:


Software tools:

Altera Quartus II Web Edition (13.0)

Altera Quartus Prime Lite Edition (15.1)

Verilog 'Blink' Example:

module ledtest(sys_clk,led);

input sys_clk;
output [2:0] led;
reg   [25:0] count;
reg [2:0] led = 3'b101;

always @(posedge sys_clk)
      count <= count + 1;
      if(count == 26'b11_1111_1111_1111_1111_1111_1110)
         led <= ~led;
         led <= led;




Disclaimer: Libraries, example code, and diagrams are provided as an additional free service by Hobby Components and are not sold as part of this product. We do no provide any guarantees or warranties as to their accuracy or fitness for purpose.

Descriptions and diagrams on this page are copyright Hobby Components Ltd and may not be reproduced without permission.

You do not have the required permissions to view the files attached to this post.

Fri Aug 12, 2016 9:14 am
Display posts from previous:  Sort by  
Reply to topic   [ 1 post ] 

Who is online

Users browsing this forum: No registered users and 1 guest

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Thank you to &
Design created by Florea Cosmin Ionut.
© 2011 All contents of this site are © Hobby Components LTD